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Texas Instruments /MSP432P401M /COMP_E0 /CExCTL2

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Interpret as CExCTL2

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15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CEREF0_0)CEREF00 (CERSEL_0)CERSEL 0 (CERS_0)CERS 0 (CEREF1_0)CEREF10 (CEREFL_0)CEREFL 0 (CEREFACC_0)CEREFACC

CEREF0=CEREF0_0, CERS=CERS_0, CERSEL=CERSEL_0, CEREFL=CEREFL_0, CEREF1=CEREF1_0, CEREFACC=CEREFACC_0

Description

Comparator Control Register 2

Fields

CEREF0

Reference resistor tap 0

0 (CEREF0_0): Reference resistor tap for setting 0.

1 (CEREF0_1): Reference resistor tap for setting 1.

2 (CEREF0_2): Reference resistor tap for setting 2.

3 (CEREF0_3): Reference resistor tap for setting 3.

4 (CEREF0_4): Reference resistor tap for setting 4.

5 (CEREF0_5): Reference resistor tap for setting 5.

6 (CEREF0_6): Reference resistor tap for setting 6.

7 (CEREF0_7): Reference resistor tap for setting 7.

8 (CEREF0_8): Reference resistor tap for setting 8.

9 (CEREF0_9): Reference resistor tap for setting 9.

10 (CEREF0_10): Reference resistor tap for setting 10.

11 (CEREF0_11): Reference resistor tap for setting 11.

12 (CEREF0_12): Reference resistor tap for setting 12.

13 (CEREF0_13): Reference resistor tap for setting 13.

14 (CEREF0_14): Reference resistor tap for setting 14.

15 (CEREF0_15): Reference resistor tap for setting 15.

16 (CEREF0_16): Reference resistor tap for setting 16.

17 (CEREF0_17): Reference resistor tap for setting 17.

18 (CEREF0_18): Reference resistor tap for setting 18.

19 (CEREF0_19): Reference resistor tap for setting 19.

20 (CEREF0_20): Reference resistor tap for setting 20.

21 (CEREF0_21): Reference resistor tap for setting 21.

22 (CEREF0_22): Reference resistor tap for setting 22.

23 (CEREF0_23): Reference resistor tap for setting 23.

24 (CEREF0_24): Reference resistor tap for setting 24.

25 (CEREF0_25): Reference resistor tap for setting 25.

26 (CEREF0_26): Reference resistor tap for setting 26.

27 (CEREF0_27): Reference resistor tap for setting 27.

28 (CEREF0_28): Reference resistor tap for setting 28.

29 (CEREF0_29): Reference resistor tap for setting 29.

30 (CEREF0_30): Reference resistor tap for setting 30.

31 (CEREF0_31): Reference resistor tap for setting 31.
CERSEL

Reference select

0 (CERSEL_0): When CEEX = 0, VREF is applied to the V+ terminal; When CEEX = 1, VREF is applied to the V- terminal

1 (CERSEL_1): When CEEX = 0, VREF is applied to the V- terminal; When CEEX = 1, VREF is applied to the V+ terminal
CERS

Reference source

0 (CERS_0): No current is drawn by the reference circuitry

1 (CERS_1): VCC applied to the resistor ladder

2 (CERS_2): Shared reference voltage applied to the resistor ladder

3 (CERS_3): Shared reference voltage supplied to V(CREF). Resistor ladder is off
CEREF1

Reference resistor tap 1

0 (CEREF1_0): Reference resistor tap for setting 0.

1 (CEREF1_1): Reference resistor tap for setting 1.

2 (CEREF1_2): Reference resistor tap for setting 2.

3 (CEREF1_3): Reference resistor tap for setting 3.

4 (CEREF1_4): Reference resistor tap for setting 4.

5 (CEREF1_5): Reference resistor tap for setting 5.

6 (CEREF1_6): Reference resistor tap for setting 6.

7 (CEREF1_7): Reference resistor tap for setting 7.

8 (CEREF1_8): Reference resistor tap for setting 8.

9 (CEREF1_9): Reference resistor tap for setting 9.

10 (CEREF1_10): Reference resistor tap for setting 10.

11 (CEREF1_11): Reference resistor tap for setting 11.

12 (CEREF1_12): Reference resistor tap for setting 12.

13 (CEREF1_13): Reference resistor tap for setting 13.

14 (CEREF1_14): Reference resistor tap for setting 14.

15 (CEREF1_15): Reference resistor tap for setting 15.

16 (CEREF1_16): Reference resistor tap for setting 16.

17 (CEREF1_17): Reference resistor tap for setting 17.

18 (CEREF1_18): Reference resistor tap for setting 18.

19 (CEREF1_19): Reference resistor tap for setting 19.

20 (CEREF1_20): Reference resistor tap for setting 20.

21 (CEREF1_21): Reference resistor tap for setting 21.

22 (CEREF1_22): Reference resistor tap for setting 22.

23 (CEREF1_23): Reference resistor tap for setting 23.

24 (CEREF1_24): Reference resistor tap for setting 24.

25 (CEREF1_25): Reference resistor tap for setting 25.

26 (CEREF1_26): Reference resistor tap for setting 26.

27 (CEREF1_27): Reference resistor tap for setting 27.

28 (CEREF1_28): Reference resistor tap for setting 28.

29 (CEREF1_29): Reference resistor tap for setting 29.

30 (CEREF1_30): Reference resistor tap for setting 30.

31 (CEREF1_31): Reference resistor tap for setting 31.
CEREFL

Reference voltage level

0 (CEREFL_0): Reference amplifier is disabled. No reference voltage is requested

1 (CEREFL_1): 1.2 V is selected as shared reference voltage input

2 (CEREFL_2): 2.0 V is selected as shared reference voltage input

3 (CEREFL_3): 2.5 V is selected as shared reference voltage input
CEREFACC

Reference accuracy

0 (CEREFACC_0): Static mode

1 (CEREFACC_1): Clocked (low power, low accuracy) mode

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data